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ABS System IC
TLE 6210 TLE 6211
1
1.1
* * * * * * * * *
Overview
Features
5 V, 800 mA linear regulator Undervoltage/overvoltage reset Undervoltage and overvoltage logout Digital watchdog supervision for 2 Microcontrollers (motor) relay driver (valve) relay driver Inverted or non inverted lamp relay driver Enable output Overtemperature and overcurrent protection Ordering code on request on request on request
P-DSO-20-10, -12, -16
Type TLE 6210 C TLE 6210 G TLE 6211 G
Package/Shipment Bare dice P-DSO-20-12, Tape and Reel P-DSO-20-12, Tape and Reel
1.2
Functional Description
The TLE 6210 and TLE 6211 are integrated circuit consisting of a 5 V voltage regulator with 800 mA current capability, different relay driver outputs and supervision logic. The supervision logic watches the input voltage and the regulator output voltage both for over-voltage and under-voltage. In addition two window watchdogs supervise the correct operation of 2 independent watchdog signals, e.g. from two Microcontrollers. The TLE 6210 and TLE 6211 are designed especially for the severe conditions of ABS/ ASR applications in an automotive environment.
V1.2 Data Sheet
1
2002-08
TLE 6210 TLE 6211
Overview
1.3
Block Diagram
UST UZP Linear Regulator USTS
UZP UVLO and OVLO detection
USTS under- and overvoltage reset detection Reset detection RES1
MR
RES2
SupervisionLogic
EN PGND VR
PGND
WD1 Window watchdog
SILA
WD 2
PGND NSILA SIA
PGND MRA
Oscillator PGND
Clock supervision
Charge Pump GND
UCP
TLE6210-block AD 20.09.01
Figure 1
Block Diagram
V1.2 Data Sheet
2
2002-08
TLE 6210 TLE 6211
Pin / Pad Configuration
2
Pin / Pad Configuration
20
11
1
10
Figure 2
Pin Configuration P-DSO-20-12
Layout
RES2 RES1 UCP UZP USTS UST EN
VR
SILA NSILA GNDP GNDP GND
MR WD2 WD1 GND SIA MRA
Figure 3
Chip-Layout
V1.2 Data Sheet
3
2002-08
TLE 6210 TLE 6211
Pin / Pad Configuration Pin / Pad Definitions and Functions
Pin Number TLE 6210 G 1 2 3 4 TLE 6211G 1 2 3 4 Symbol / Pad Name GND N.C. Function
Power GND connection Not Connected Supply Voltage; reverse protection diode is required Charge Pump Capacitor pin; An external capacitor is the energy storage for the charge pump Reset Output 1; open collector output with integrated pull-up resistor. A high indicates normal operation; function identical to RES2 Enable Output; open collector; low indicates an error condition Reset Output 2; open collector output with integrated pull-up resistor. A high indicates normal operation; function identical to RES1 Valve Relay Output; open drain output Lamp Output; open drain output; For TLE 6210 CW only Inverted Lamp Output; open drain output; For TLE 6211 CW only Power Ground connection Power Ground connection Motor Relay Output; open drain output Lamp Control Signal Input; controls SILA/NSILA; a logic high switches SILA off and NSILA on Watchdog Input 2 Motor Relay Control Input; A logic High switches MR on Watchdog Input 1 Logic Ground Sense input for UST supervision 5 V Linear Regulator Output Ground Connection The lead frame connects the pins 1, 10, 11 and 20 to the backside metallization. 4 2002-08
UZP UCP
RES1
5
5
6 7
6 7
EN RES2
8 9 - 10 11 12 13 14 15 16 17 18 19 20
8 - 9 10 11 12 13 14 15 16 17 18 19 20
VR SILA NSILA GND GND MR SIA WD2 MRA WD1 GND
USTS UST
GND GND
Backside metallization
V1.2 Data Sheet
TLE 6210 TLE 6211
Electrical Characteristics
3
3.1
# M1
Electrical Characteristics
Absolute Maximum Ratings -40 C Tj 150 C
Parameter Supply Voltage Symbol Limit Values Unit Conditions min. max. 20 26.5 35 V V V - 0 0 0
UZP
0 < tp 5 min.; -40 C 80 C 0 < tp 200 ms; f < 0.067 Hz; n 360 cycles 0 < tp 50 ms; 0 < fp 1 Hz; n 36000 cycles
0
35
V
-1.5 M2 M3 M4 M5 M6 M7 M8 M9 Supply Voltage variation Output voltage at SILA Output voltage at NSILA Output voltage at RES1, RES2 Output voltage at EN Input Voltage at WD1, WD2, MRA, SIA Voltage UCP dUZP/dt - - - - -0.5 -0.5 -0.5 -0.5 -55 -40 Output voltage at VR, MR UVR, UMR
-
V V V V V V V V
tp = 2 s
VR, MR-DMOS off SILA-DMOS off NSILA-DMOS off - - - - - continuos short term (< 50 h over lifetime)
|10|
60 42 42 7 7 7 20 150 150 175
V/ms -
M10 Storage Temperature M11 Junction Temperature
USILA UNSILA URES1 URES2 UEN UWD1, UWD2 UMRA, USIA UCP Tstg Tj
C C C
V1.2 Data Sheet
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2002-08
TLE 6210 TLE 6211
Electrical Characteristics
3.1
#
Absolute Maximum Ratings (cont'd) -40 C Tj 150 C
Parameter Symbol - Limit Values Unit Conditions min. max. according to EIA/JESD 22-A 114B
M12 ESD
4000 - 2000 -
M13 Life Time
V V h
UZP, MR, EN,
VR, SILA, all other pins ambient temperature range:
tb
10000 -
-40C 2% -20C 10% 25C 60C 80C 24% 34% 24%
100C 5% >120C 1%
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
V1.2 Data Sheet
6
2002-08
TLE 6210 TLE 6211
Electrical Characteristics
3.2
# F1
Functional Range
Parameter Supply voltage SymLimit Values bol min. typ. max. Unit V V V Conditions -
UZP
4.5 - -
14.0 - -
18 26.5 4.5
t < 5 min. UST 0.3 V;
Reset = Low; Enable = Low; VR and MR off
F2
Input capacitor Case Temperature Junction Temperature
CUZP 0.33
3.3
-
mF
TU = 20 C UN = 63 V
Typ. = MKT
F3 F4 F5 F6
TC Tj
-40 -40 - - -
- - - 40 -
125 150 175 - 2.4
C C C
K/W K/W
P-DSO-20-12 life time short time1) P-DSO-20-12 minimum footprint P-DSO-20-12
Thermal resistance Rthja junction-ambient Thermal resistance Rthjc junction-case
1)
Parameter may deviate in the temperature range Tj = 150 C ... 175 C Total operation time max. 50 h for temperature range Tj > 150 C
Within the functional range the device works according to the functional description. However parameters may exceed the values given in the Characteristics.
V1.2 Data Sheet
7
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4
4.1
Block Description and Electrical Characteristics
General
Characteristics 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit Conditions bol min. typ. max. - 7 15 mA
4.1.1 Power consumption IUZP regulator
UZP = 16 V, IUST = 800 mA,
VR on, SILA on, EN, RES1, RES2 = High
4.1.2 Overtemperature Tab protection threshold
150
-
-
C
Tj > Tab
4.2
Oscillator
A 16 kHz oscillator is used as time base for the 1 kHz clock. An independent clock supervision circuit supervises the oscillator. If the oscillator clock is missing the error flag is set. Characteristics Internal Oscillator 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Limit Values Unit Conditions Symbol min. typ. max.
4.2.1 Frequency 4.2.2 Clock supervision 4.2.3 Logic time base
fOSZ
14.4 13.6
16 - 120 1
17.6 18.4 - 1.1
kHz UZP 6 V kHZ 4.7 V UZP < 6 V
tCLUE - tCLK
0.9
ms
ms
error if tLow or tHigh > tCLUE Period
V1.2 Data Sheet
8
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.3
Charge Pump
The integrated charge pump requires an external capacitor at pin UCP. The charge pump voltage is typically 15 V. It is internally used for the voltage regulator only. It is only intended for internal function and may not be used for any external loads. The output voltage is short circuit protected against the supply voltage. Characteristics Charge Pump 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit Conditions bol min. typ. max.
4.3.1 Power up time
tCP
-
10
-
ms
UZP = 6 V; CCP = 68 nF;
Load capacitor to U = 0.9 UCPmax
4.3.2 Charge pump voltage UCP 4.3.3 Frequency
- 1.4
15 3.2
22 -
V
Regulator on
fCP
MHz -
V1.2 Data Sheet
9
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.4
Voltage Regulator
The 5 V low drop linear regulator can supply up to 800 mA current. The regulator requires an output capacitor. The linear regulator is equipped with overcurrent protection and its own overtemperature protection. The linear element consists of 2 anti-serial DMOS transistors. In case of low input supply voltage this avoids discharging of the output capacitor. The output voltage UST is supervised for over- and undervoltage. UST output has to be connected externally to the sense input USTS. If over- or undervoltage condition is detected the Reset outputs RES1 and RES2 are logical low. For a detailed description of the reset logic please see Chapter 4.9. Characteristics Voltage Regulator 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified
# 4.4.1 Parameter Nominal output voltage Symbol Limit Values min. typ. max. Unit Conditions
UST
UZP = 14 V; IST = 400 mA; Output capacitor as defined in 4.4.11;
4.95 5.00 4.925 5.00 5.05 V 5.075 V 800 |50| mA mV on wafer level Tj = 25 C P-DSO-20-12 -
4.4.2 4.4.3
UST load current IST
Line variation DUST
- -
- -
Tj = 25 C; 6.0 V UZP 18 V; IST = 600 mA; capacitor as
defined in 4.4.11; dUZ/dt < 1 V/ms
V1.2 Data Sheet
10
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics Characteristics Voltage Regulator (cont'd) 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified
# 4.4.4 Parameter Load variation Symbol DUST Limit Values min. - typ. - max. |50| mV Unit Conditions
capacitor as defined in 4.4.11; dIST/dt 1 mA/ms 4.4.5 Temperature variation DUST - |50| |100| mV
Tj = 25 C; UZP = 14 V; 0 mA IST 800 mA;
UZP = 14 V; IST = ISTmax; -40 C Tj 150 C;
capacitor as defined in 4.4.11; for die mounted in a hybrid: dTU/dt 10 K/s for P-DSO-20-12: dTG/dt 5 K/min.
4.4.6
Long time drift
DUST |50| 5.25 |25|
- 4.4.7 4.4.8 Overall output UST voltage tolerance Power Supply ripple rejection Series Resistor DUSTss 4.75 -
- 5.00 -
mV V mV
M13.
UZP UZPmax.; 0 mA IST ISTmax.; -40 C Tj 150 C; tb = 10000 h, see conditions
all parameters from 4.4.1 to 4.4.6 0 Hz fUST 10 kHz; capacitor as defined in 4.4.11; 7 V UZP 24 V
4.4.9
RDSon
- -
- -
1.7 2.7
W W
Tj = 25 C Tj = 150 C UCP > 15 V; UZP = 6 V; IST = 800 mA
4.4.10 Maximum output IK current (output shorted) 4.4.11 Load capacitor at CUST output UST Z 4.4.12 UST off voltage 4.4.13 Clamping voltage
0.8
-
1.6
A
UCP > 15 V; UST = 0 V; 4.5 V UZP 18 V TU = 20 C; UN = 25 V; Type ETQW Roederstein f = 100 kHz; TU = 20 C IST = 0 mA
clamping voltage at
3.3 - 5.5
- 4 - -
150 - 400 7
mF W mV V
USTRest - UZST
I = 100 mA
V1.2 Data Sheet
11
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.5
Enable-Output EN
The open collector enable output EN informs the system about any error condition. Any error except a detected supply under-voltage will set the EN output Low. Of cause for long under-voltage at the supply line, soon the UST output capacitor will be discharged and this will cause UST under-voltage and therefore EN Low. The time depends on the load and the output capacitor. The EN is an open collector output. It is short circuit protected to UST. After power up when the first watchdog edges at WD1 a WD2 are detected the Enable output is switched into High state. Characteristics EN Output 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol Limit Values min. 4.5.1 Output Low voltage 4.5.2 Reverse current typ. - - - max. 0.4 0.2 5 V V - - - Unit Conditions
UL IR
mA
IL 10 mA IL 1 mA UEN = 5 V
V1.2 Data Sheet
12
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics Power Driver The TLE 6210/TLE 6211 includes 3 open drain outputs for loads up to 0.5 A: The two drivers VR and MR are intended for (valve and motor) relays, while the SILA/NSILA output is designed for a lamp. In the TLE 6210 GW the SILA output is available. The output goes low if the supply voltage UZP is no longer available - the DMOS is switched on automatically. In the TLE 6211 GW the NSILA has the inverted polarity related to SILA. In bare dice both outputs SILA and NSILA can be used. .
4.6
Valve Relay Output VR
The valve relay output VR is switched On after the power up reset and valid watchdog signals. The driver has an open drain configuration and can supply up to 500 mA. The output is protected against overtemperature and overcurrent. The output is short circuit protected to UZ. The output stage is equipped with its own overtemperature protection. In case of overvoltage at the supply UZP the output is switched off. However the output is not protected against overvoltages caused by switching inductive loads. Therefore externally a free wheeling diode is required as shown in the application diagram. The valve relay output VR is controlled by the internal supervision logic. If any watchdog errors or supply over-voltage is detected or the 5 V regulator is out of range, the VR is switched off (please see also Table 1 on Page 19 and Table 2 on Page 28). Characteristics Relay Driver Output VR 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol Limit Values min. typ. - - - - - - - max. 1.2 2.4 - 0.5 2 - V Unit Conditions
4.6.1 Saturation Voltage 4.6.2 On state resistance 4.6.3 Overload detection current 4.6.4 Output leakage current 4.6.5 Overtemperature shutdown threshold
UDS
RDSon - IK IR TK
500 - - 150
W
mA mA mA
Rlast 35 W; IL 0.5 A; 6 V UZP 16 V Tj = 150 C; IL = 0.5 A; UZP = 6 V
-
UA 16 V 16 V < UA 60 V
-
C
V1.2 Data Sheet
13
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.7
Motor Relay Driver
The motor relay driver MR is controlled by the MRA input signal and the internal control logic. A logic High at the MRA input switches the MR low side switch on, a logic Low signal switches it off. However the supervision logic overrules the MRA input condition. Please see also Table 1 on Page 19 and Table 2 on Page 28. The output is an open collector output and can sink up to 500 mA. It is protected against overtemperature and overcurrent and short circuit prove to UZ. Even the output is switched off by the supervision logic at UZP overvoltage externally a free wheeling diode is required to protect the output against switching off inductive loads. Characteristics Relay Driver Output MR 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol Limit Values min. typ. - - - - - - - max. 1.2 2.4 - 0.5 2 - V Unit Conditions
4.7.1 Saturation Voltage 4.7.2 On state resistance 4.7.3 Overload detection current 4.7.4 Output leakage current 4.7.5 Overtemperature shutdown threshold
UDS
RDSon - IK IR TK
500 - - 150
W
mA mA mA
Rlast 35 W; IL 0.5 A; 6 V UZP 16 V Tj = 150 C; IL = 0.5 A; UZP = 6 V
-
UA 16 V 16 V < UA 60 V
-
C
V1.2 Data Sheet
14
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.7.1
Control Input MRA
The logic inputs MRA expect TTL-type signals from a m-controller with 5 V I/Os. An integrated pull-up resistor ensures that an open input is read High. Characteristics Control Inputs MRA 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # 4.7.6 4.7.7 4.7.8 4.7.9 Parameter Internal pull-up resistor to UST Input voltage Low SymLimit Values Unit Conditions bol min. typ. max.
RWD
10 -0.3 2.0 - -
20 - - - -
40 1.0
kW
V V
0 V UE UST + 0.3 V
- -
UL Input voltage High UH
Input current
UST
+ 1.0
IH
|5|
1.0
mA
mA
UE = UST UST < UE UST + 1 V
V1.2 Data Sheet
15
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.8
Error Lamp Output SILA and Lamp Relay Output NSILA
The SILA output is a 300 mA open collector output. It is available in the TLE 6210 G. SILA is a self-on output: It is switched on if the supply voltage is missing. The TLE 6211 G is equipped with the logically inverted NSILA output. NSILA is a 30 mA open collector output. It is intended to drive the lamp relay. In the dice version TLE 6211 C both outputs can be used. Both SILA and NSILA are intended to control a warning lamp. The output is controlled by the internal supervision logic and control signal at the SIA pin. A logic High at the SIA input switches SILA off and NSILA on. The supervision logic will switch on SILA if a watchdog timing violation is detected or the output voltage UST is out of range. Table 1 on Page 19 and Table 2 on Page 28 give an overview on the different errors. The SILA output is equipped with its own overtemperature protection. Characteristics Lamp Driver Output SILA 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit Conditions bol min. typ. max.
4.8.1 Saturation voltage 4.8.2 Overload detection current 4.8.3 Output leakage current
USILA -
-
- - - - - - -
2.5 2.5 - 0.1 4 4.7 -
V mA mA mA V
I = 300 mA; UZP 6 V I = 300 mA; UZP = 0 V
-
IK IR
300 - - 1 150
4.8.4 Threshold voltage for UZP automatic ON 4.8.5 Overtemperature shutdown threshold
TK
C
USILA 16 V 16 V < USILA < 42 V USILA 2.5 V; I = 300 mA UZP 6 V
V1.2 Data Sheet
16
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics Characteristics Lamp-Relay Driver Output NSILA 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol Limit Values min. typ. - - - max. 33 - 10 Unit Conditions
4.8.6 On state resistance RDSon - 4.8.7 Overload detection current 4.8.8 Output leakage current
W
mA
Tj = 150 C; I = 30 mA; UZP 7 V
-
IK IR
30 -
mA
UNSILA 42 V
4.8.1
Control Input SIA
The logic inputs SIA expect TTL-type signals from a m-controller with 5 V I/Os. An integrated pull-up resistor ensures that an open input is read High. Characteristics Control Inputs SIA 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # 4.8.9 Parameter Internal pull-up resistor to UST Limit Values Unit Conditions Symbol min. typ. max.
RWD
10 -0.3 2.0 - -
20 - - - -
40 1.0
kW
V V
0 V UE UST + 0.3 V
- -
UL 4.8.11 Input voltage High UH
4.8.10 Input voltage Low 4.8.12 Input current
UST
+ 1.0
IH
|5|
1.0
mA
mA
UE = UST UST < UE UST + 1 V
V1.2 Data Sheet
17
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics Supervision The TLE 6210 and TLE 6211 are equipped with a complex supervision logic. The input voltage and the regulator output voltage is supervised. In addition two m-controller are supervised by independent watchdog circuits.
4.9
Overvoltage and Undervoltage
Both the supply voltage UZP and the output voltage UST are supervised for over- and undervoltage. In case any undervoltage or overvoltage condition at UST or UZP is detected, the reset outputs RES1 and RES2 are switched to low state. RES1 and RES2 are not controlled by the watchdog logic. To supervise the output voltage UST an independent bandgap from the reference bandgap is used. The reset outputs RES1 and RES2 are together controlled by the UST reset logic and the supply undervoltage lockout (UVLO) and overvoltage lockout (OVLO). A logic High at the RES1 and RES2 indicates normal operation. The outputs are open collector type outputs with integrated pull-up resistors to UST. Even when the UST voltage drops, the reset outputs RES1 and RES2 remain low (< 0.4 V). Both undervoltage and overvoltage detection of UST and UZP use a voltage hysteresis to avoid any reset toggling. Undervoltage and Overvoltage Detection UST The UST output voltage has to be externally connected to the USTS sense input. To be able to detect also wrong output voltages causes by a malfunction of the related bandgap reference for supervision an independent bandgap is used. As soon as any reset condition is detected the RES1 and RES2 go low.
4.9.1
Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO)
The supply voltage UZP is supervised as well. If the voltage rises above the upper threshold value of 19.5 V reset is asserted. When an undervoltage occurs, after some time the output voltage will drop below the reset threshold and a reset is asserted. The undervoltage lockout is only valid during power up. Both the OVLO and the UVLO threshold use a hysteresis to avoid reset glitches. In addition the OVLO is digitally filtered. Overvoltage below 2 to 3 clock cycles (equals typical 2 s or 3 s) are neglected to avoid resetting the system when any inductive load is switched off.
V1.2 Data Sheet
18
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics When the undervoltage condition at UST or UZP is no longer detected a reset reaction time of typical 52 ms (52 clock cycles) is started. After this time the reset signal is set high. Table 1 Truth Table Overvoltage and Undervoltage Supervision
The table assumes that no other error is detected, especially no watchdog failure and no clock failure. Supply voltage Regulator SILA Voltage NSILA MR VR EN RES 1 Regulator RES 2 H L H L H L ON ON ON OFF ON OFF
UZP
ok ok normal undervoltage undervoltage overvoltage
UST
ok undervoltage overvoltage undervoltage ok x = SIA = not SIA = not MRA L L L Z Z Z Z Z Z L Z Z Z L Z Z L L Z* H Z*
= SIA = not SIA not MRA =L Z Z
Z: high impedance * In the application the voltage is undefined as regulator is off
V1.2 Data Sheet
19
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.9.2
UZP
12V 5.3V
Under- and Overvoltage Reset Behavior
t UST
5V 4.6V
t
52ms
RES1
5V
t RES2
5V
t
Figure 4 Characteristics Supervision of UZP, UST 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Symbol Limit Values min. typ. max. Unit Conditions
UZP-Undervoltage
4.9.1 4.9.2
UZP undervoltage UZPU threshold UZP undervoltage UH
hysteresis
5.2 20
5.3 -
5.4 50
V mV
UST off UZPU(ON) = UZPU(OFF) + UH1)
UZP-Overvoltage
4.9.3
UZP overvoltage
threshold
UZUE
18.75 19.5
20.25 V
Outputs NSILA, VR, MR, UST off
V1.2 Data Sheet
20
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics Characteristics Supervision of UZP, UST (cont'd) 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # 4.9.4 4.9.5 Parameter Symbol Limit Values min. typ. - - - - - max. 1.0 3 3.4 3 3.4 V 0.5 2 1.8 2 1.8 Unit Conditions
UZP overvoltage
hysteresis
UH ton toff
UZP overvoltage
filter
tCLK threshold ms
UH = UZUE(on) - UZUE(off) UZP overvoltage
tCLK UZP < overvoltage ms threshold
UST-Undervoltage
4.9.6 4.9.7
UST undervoltage USTU threshold UST undervoltage UH hysteresis
4.5 20
4.6 -
4.7 50
V mV
RES1, RES2 = low
USTU(on) = USTU(off) + UH1)
UST-Overvoltage
4.9.8 4.9.9
UST overvoltage
threshold
UST overvoltage hysteresis
USTUE UH ISTS
5.3 20 0.94
5.4 - 1.5
5.5 50 2.2
V mV mA
Error flag is set
4.9.10 USTS input current
USTUE(ON) = USTUE (off) - UH1) USTS = 6 V
Reset timing
4.9.11 Reset delay time
tRH
- 52 46.35 52
- tCLK 58.85 ms UZP 5.4 V UST 4.75 V
1)
Hysteresis guaranteed by design.
V1.2 Data Sheet
21
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.10
Reset Outputs RES1, RES2
The two reset outputs RES1 and RES2 are open collector outputs with integrated pullup resistor of typical 10 kW to UST. Both outputs are protected against short circuits to UST. Characteristics RES1 and RES2 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit Conditions bol min. typ. max.
4.10.1 Output low voltage 4.10.2 Output high voltage 4.10.3 Internal pull-up resistor to UST
UL
- -
- - - 10
0.4 0.4
V V V
UH
UST
- 0.1
UST
20
IL = 0.8 mA; UST = 1.8 V IL = 2 mA; UST = 4.5 V 1.8 V UST 4.5 V RL 10 MW
0 V UA UST + 0.3 V
RRES 5
kW
V1.2 Data Sheet
22
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.11
Watchdog
To supervise the operation of 2 m-processors watchdog logic for two input signals is integrated. The logic expects at each WD1 and WD2 rectangular signals with 10 ms high and 10 ms low time. Deviations from the expected time are counted as errors and influence the output signals. A digital filter suppresses noise or pulses below 3 clock cycles (typ. 3 ms). The detection ciruit is described in Figure 12. After power up and 1or 2 valid watchdog edges the WD logic enables the output Drivers.
1 WD1 1 0 1 WD2 0
2
10ms
EN
1 0 3* tCLK after the 2nd WD-edge (falling edge)
wd-start-up-with Low AD 04/02
Figure 5
Enable output EN after correct watchdog signals at WD1 and WD2 are present; WD1 and WD2 start with logic Low
10ms 1 WD1 1 0 1 WD2 0 2
EN
1 0 3 * tCLK after 1st. WD edge
wd-start-up-with High AD 04/02
Figure 6
Enable output EN after correct watchdog signals at WD1 and WD2 are present; WD1 and WD2 start with logic High
23 2002-08
V1.2 Data Sheet
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
The logic expects the time between two clock edges between 3 and 15 clock-cycles. If this window is not met, the outputs VR, MR and NSILA are switched off, SILA is switched on and the enable output goes low. An internal counter ( seeFigure 12) includes a 4 bit counter. Each time the value 15 is reached a dominant counter reset signal is generated at the output "=15". This pulse is generated continuously at t = (15+3) T1 + n * (16*T1) after the last valid watchdog pulse was detected. When internal resets and watchdog edges occur at the same time, the internal reset is dominant.
10ms 1 WD1 0
t > 16 *tCLK
1 WD2 0
1 EN 0 15* tCLK + Delay = 15* tCLK + 3* tCLK Delay (3* tCLK)
wd-controls-en-2 AD 04/02
Figure 7
Missing watchdog signals cause EN low
V1.2 Data Sheet
24
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
10ms 1 WD1 0
t < 15 *tCLK
1 WD2 0 15*tCLK Delay (3* tCLK) 1 EN 0 Delay (3* tCLK) 15*tCLK + Delay = 15*tCLK + 3* tCLK wd-controls-en AD 03/02
Figure 8
Missing watchdog signals cause EN low
10ms 1 WD1 0
WD Signal not detected
1 WD2 0
1 EN 0 (15+3) * tCLK 1 Counter Reset 0 16* tCLK
wd-missing AD 03/02
Figure 9
Timing diagram - any watchdog signal missing causes a High signal at the output "=15" (Counter reset). This signal sets back the logic
V1.2 Data Sheet
25
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics Any watchdog high or low time above 15 ms influences the enable (EN) and the VR output.If the time after the last watchdog edge exceeds 120 clock cycles - typical 120 ms- an error flag is set. This flag can only be removed by powering down the IC.
10ms 1 WD1 0
1 WD2 0
1 EN 0 (15+3) * tCLK 1 0 16 * tCLK 1 set error flag 0 112 * tCLK + Delay = 112 * tCLK+ 3 * tCLK )
Counter reset
set-error-flag AD 03/02
Figure 10
Missing watchdog signals for more than 120 * tCLK (typ. 120ms) sets the failure register
An integrated pull-up resistor to UST in the WD1 and WD2 inputs ensures to detect a permanent logic High in case the input is open.
V1.2 Data Sheet
26
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics Characteristics WD1, WD2 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter SymLimit Values Unit bol min. typ. max. Conditions
4.11.1 Internal pullup resistor to UST
RWD
10 -0.3 2.0 - -
20 - - - -
40 1.0
kW
V V
0 V UE UST + 0.3 V
- -
4.11.2 Input voltage Low UL 4.11.3 Input voltage High UH 4.11.4 Input current
UST
+ 1.0
IH
|5|
1.0
mA
mA
UE = UST UST < UE UST + 1 V
Characteristics Watchdog 6 V UZP 18 V, -40 C Tj +150 C, if not otherwise specified # Parameter Limit Values Symbol min. typ. max. 1 - 2 - Unit Conditions
4.11.5 Release tON reaction time
tCLK Number of valid Watchdog input clock edges tCLK The distance between clock edges is at least tpulse
equals: periodically pulse
tpulse - 4.11.6 Closed window time
3
2.25 3 1.8 3
4.11.7 Open tVR window time -
3.3 3.3
-
ms ms
15
tCLK if the edge distance Dt > tVR, VR is switched off ms
equals
13.5 15
4.11.8 Error flag detection
17.6
-
tFSP
-
120
108
120
132
tCLK if Dt > tFSP, the error flag is set. equals ms
V1.2 Data Sheet
27
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
4.11.1
Watchdog Logic
Table 2 and Figure 11 show the watchdog logic. figure 12 shows the logic implementation Watchdog WD1, Clock WD2 Time between Edges ok < 3 * tCLK > 15 * tCLK > 120 * tCLK ok Table 2 ok ok ok ok SILA NSILA MR VR EN RES1/2 Error Flag
= SIA = not SIA = not MRA L L L Z Z Z Z Z Z
L Z Z Z
Z L L L
H H H H H
L L L H H
error L Z Z Z L Watchdog and Clock Supervision Truth Table
The table assumes that no other error is detected, especially no undervoltage or overvoltage at the supply and regulator output. Z: High impedance
V1.2 Data Sheet
28
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
t1 WD1
t2
t3
t4
t5
t WD2
t EN
t VR
t MR
t SILA
t NSILA
t
Figure 11
Watchdog Violation Reaction
t1: t2: t3: t4: t5:
No watchdog signals at WD1 or WD2 Normal operation. EN is going high after the first watchdog edges at WD1 and WD2 are detected. Watchdog open window time exceeded: but below 120 *tCLK (typ. 120 ms). Error Flag is not set. Watchdog time too short (below closed window time) Normal operation
V1.2 Data Sheet
29
2002-08
TLE 6210 TLE 6211
Block Description and Electrical Characteristics
1 CLK Q0 Q1 Q2 Q3 Q4 Q5
WD
6 BIT SHIFT REGISTER
&
1
RESQ
&
wd-detect AD06/02
1
Figure 12
Logic Diagram: Detection of Watchdog Edges.
The watchog signal is clocked through the shiftregister. The output condition of the edge detection circuit above is true for register state 111000 and 000111. 3 clks after the rising edge or falling edge of WDx the logic below will get a pulse of 1 clk length.
overvoltage at UST (active H)
CLK
WD1 CLK
J
Q CLK C & 1 1 1 R C
Counter 120 15 =15 Set Error register
K
1
sets VR high ohmic; ENQ on
CLK
WD2
J
Q C "1" D C Q R R Q D C Q Q
CLK K
1
1
Undervoltage reset (low active)
TLE6210-wd-logic AD 04/02
Figure 13
Block Diagram Watchdog Logic
30 2002-08
V1.2 Data Sheet
TLE 6210 TLE 6211
Application Diagram
5
Application Diagram
TLE6210/1
U
Bat
UST Linear Regulator USTS
UZP
UST 5V
U
Bat
U
Bat
UZP UVLO and OVLO detection
USTS under- and overvoltage reset detection Reset detection RES1 to Microcontroller to Microcontroller
MR
RES2
SupervisionLogic
EN PGND VR to Microcontroller
U
Bat
U
Bat
PGND
WD1 Window watchdog
from Microcontroller
SILA
WD 2
from Microcontroller
PGND NSILA SIA from Microcontroller
PGND MRA from Microcontroller
Oscillator PGND
Clock supervision
Charge Pump GND
UCP CCP 68nF GND TLE6210-app-diagram AD 11.7.02
Power GND
Logic GND
Figure 14
Application Diagram
V1.2 Data Sheet
31
2002-08
TLE 6210 TLE 6211
Package Outlines
6
Package Outlines
P-DSO-20-12 (Plastic Dual Small Outline Package)
3.5 MAX.
0 +0.1 3.25 0.1
11 0.15 1)
B
0.25
+0.07 -0.02
1.2 -0.3
2.8
1.27
15.74 0.1 (Heatslug) 0.25 M A 20x
11
1.3
6.3 (Mold)
14.2 0.3 11 20
0.1
Heatslug 0.95 0.15 0.25 B
0.4 +0.13
20
Index Marking Heatslug
1 x 45
1
10
10
13.7 -0.2 (Metal)
1
15.9 0.15 1) (Mold)
1)
A
Does not include plastic or metal protrusion of 0.15 max. per side
GPS05791
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device V1.2 Data Sheet 32
3.2 0.1 (Metal)
Dimensions in mm 2002-08
5.9 0.1 (Metal)
5 3
TLE 6210 TLE 6211
Revision History
Version V0.0
Date
Major Changes Device is a replacement of the TLE 5200/TLE 5201 with the following deviations form the specification from 1998-01-21. Devices are only available in the P-DSO-20-12 package or as bare dice The data sheet structure was changed and some chapters where moved. Parameter reference numbers are changed now: TLE 5200/01 TLE 6210/11 * Control input SIA 1.x 4.8.x * Control input MRA 1.x 4.7.x * Enable 2.x 4.5.x * Reset outputs 3.x 4.10.x * SILA/NSILA 4.x 4.8.x * VR 5.x 4.6.x * MR 5.x 4.7.x * Voltage supervision 6.x 4.9.x * Oscillator 7.x 4.2.x * Watchdog 8.x 4.11.x * Charge Pump 9.x 4.3.x * 5 V Regulator 10.x 4.4.x * General information 10.x 4.1.x Absolute Maximum Ratings: Digital I/Os (reference M6, M7, M8) changed to -0.5 to 7 V
2002-08 Advanced Information Data Sheet TLE 6210, TLE 6211
V0.1 V0.2
2001-11 Update truth table 2002-04 increase error flag detection time tFSP from 112 clock cycles to 120 clock cycles (parameter 4.11.8) Add of logic block diagram (figure 12) and watchdog timing diagrams (figure 5 to 10)
V1.2 Data Sheet
33
2002-08
TLE 6210 TLE 6211
Revision History Version V1.0 Date Major Changes
2002-07 Data sheet Remove pad / chip information from the datasheet ESD value SILA, MR, VR,UZP 4kV Update typ. value 4.3.3 Extend and correct block description at chapters 4.4; 4.6; 4.7; 4.8 Table 1: SILA function at overtemperature changed Table 2: timings as a function of tCLK Figure 11, t3: corect timing Chapter 4.11: Extend description; add figure 12: Detection of watchdog edges Appplciation diagram: replace free wheeling zener diodes at MR and VR relay by normal diodes. 2002-07 change device suffixes: bare dice: TLE621x C packaged: TLE621x G 2002-08 Table 1 and text chapter 4.8: correct NSILA at overvoltage Change long term drift 4.4.6 to 10000h Add a more detailed description to figure 12.
V1.1
V1.2
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing.
V1.2 Data Sheet
34
2002-08
TLE 6210 TLE 6211
Edition 2002-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2002.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
V1.2 Data Sheet
35
2002-08

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